|Job Role||Software Intern|
Cadence Design Systems, Inc. is an American multinational electronic design automation (EDA) software and engineering services company, founded in 1988 by the merger of SDA Systems and ECAD, Inc. The company produces software, hardware and silicon structures for designing integrated circuits, systems on chips (SoCs) and printed circuit boards.
- Must have completed BE/B Tech from a recognised university
- Should have an aggregate of 60% through out academics
- Must have experience with Hardware Design, Verification
- Should have experience in Verilog/System Verilog/UVM/C
- Must have working experience with standard protocols such as USB, Ethernet and Display Port will be helpful
- Must have experience with development and verification using SV, UVM and C will be a plus.
- Should requires leading VIP product development and becoming technical expert in protocol and standard methodologies such as UVM.
- Must require excellent communication skills to interact with multiple product groups within Cadence and the ability to ramp up on new technologies quickly and independently.
- Candidate is expected to have familiarity with c, SV based verification environment and must possess good analytical and communication skills
- Should have experience with Scripting Languages – like Perl, TCL, Python would be a huge plus.
- Must have knowledge of Distributed Processing, Cloud Computing and Machine Learning would be a huge plus.
- Must have good understanding of CMOS concepts.
- Candidate would assist in product validation role for Custom IC Layout tools.
- Should have knowledge of any scripting language like TCL/Perl will be preferred
- Must have good oral and written communication skills
- Must have experience in Host software (MVS, VM etc)
- Should have advance knowledge of Teradata, Linux, UNIX, Windows, mainframe operating systems (VM/MVS, etc.)
- Must have teradata Database experience
- Must be a logical and analytical thinker.
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