Organization : MicroSemi
Job Role : Associate Engineer
Location : Hyderabad
Qualification : BE/B Tech/ME
Experience : Freshers
Salary : Rs 3 LPA
No.of Vacancies : NA
Website : www.microsemi.com
Apply Mode : Online
Apply Date : ASAP
Microsemi agency gives a comprehensive portfolio of semiconductor and system answers for communications, defense & safety, aerospace and industrial markets. products encompass high-performance, radiation-hardened and especially reliable analog combined-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and voice processing devices; RF answers; discrete components; protection technologies and scalable anti-tamper products; power-over-Ethernet ICs and midspans; in addition to custom design competencies and services. Microsemi is centered in Aliso Viejo, Calif., and has about 3,000 personnel globally.
* Develop tests with software/firmware flow used in SoC FPGA verification
* Development of Behavioral models using Verilog and SystemVerilog
* Develop Coverage driven Verification flows
* Develop and complete block-level verification and contribute on test development for SoC FPGA fullchip level verification
* Candidate should be BE/B Tech/ME from a recognised university.
* Should have an aggregate of 60% through out academics.
* Must have hands-on project experience in RTL Verification
* Must have strong knowledge on digital fundamentals and understanding of FPGA/ custom chip flow
* Should have hands on knowledge on Verilog and SystemVerilog
* Must have good programming knowledge in C, C++ language
* Should have experience in FPGA programming and related software usage with Firmware handling knowledge is a plus
* Must have exposure to SVF and STAPL/JAM: Adaptive FPGA Programming is a plus
* Must have good Knowledge in logic design and analysis
* Should have experience with UNIX shell scripting or Perl scripting
* Must have experience in Verilog, SystemVerilog Modeling is recommended
* Must have exposure to SoC FPGA flow concepts
* Must have exposure to knowledge on System Verilog Assertions, Functional Coverage and Scoreboard development
* Should have experience with leading edge simulator tools is recommended
* Must have good analytical and problem solving skills
* Should have excellent written and verbal communication in English.
* Must have willingness to travel on short notices occasionally.
* Must be able to write verification specifications, verification plans, and documentation
* Should develop test bench and automate regression plans
* Must be responsible for simulations, verifications, and debugging of logic designs (schematics, RTL)
* Should be responsible for developing test benches , test cases and verification flow components for Soc based FPGA
* Should be self-motivated and have enthusiastic approach that will achieve any new requirements and overcome all challenges
* Must be able to work independently with minimal support and handle complex Block and Subsystem Verification platform
* Should be able to debug the logic designs for design intent and Interface with cross-functional teams and collaboration in all verification related activities