Organization : Synopsys
Job Role : Technical Intern
Location : Hyderabad
Qualification : BE/B Tech
Experience : Freshers
Salary : Rs 3.5 – 5 LPA
No.of Vacancies : NA
Website : www.fresherjobs9.com
Apply Mode : Online
Apply Date : ASAP
Synopsys, Inc provides products and offerings that speed up innovation within the global electronics market. As a chief in electronic design automation (EDA) and semiconductor intellectual property (IP), Synopsys’ complete, built-in portfolio of approach-stage, IP, implementation, verification, manufacturing, optical and discipline-programmable gate array (FPGA) solutions support handle the important thing challenges designers face comparable to energy and yield management, process-to-silicon verification and time-to-results. These technological know-how-leading solutions support give Synopsys purchasers a aggressive side in quickly bringing the first-rate merchandise to market even as lowering expenditures and agenda risk.
* Candidate should be BE/B Tech from a recognised university.
* Should have an aggregate of 60% through out academics.
* Must have knowledge of development of PDKs for Synopsys customers.
* Should provide technical assistance by writing scripts using Tcl and Python.
* Must be running QA and regression tests for developed PDKs.
* Must have development and delivery of product training material.
* Should provide technical assistance in resolving issues that need a deeper understanding of the tools.
* Must have strong Digital and Analog Design concepts.
* Should have understanding of ASIC Design flow.
* Must have knowledge of EDA tools will be a plus.
* Must have basic knowledge of UNIX and Shell scripting, hands-on experience with any scripting language like perl, python, Tcl etc is desirable.
* Should work on a designated project (s) independently and / or with minimum supervision
* Should be able to assist the Consultants with developing scripts for automation of process, tools, and frameworks.
* Must have basic knowledge of SRAM bitcell
* Should have basic knowlwedge of memory architecture
* Must have basic knowledge of memory timing arcs