Organization : Synopsys
Job Role : Technical Intern
Location : Noida
Qualification : BE/B Tech
Experience : Freshers
Salary : Rs 3.5 – 5 LPA
No.of Vacancies : NA
Website : www.fresherjobs9.com
Apply Mode : Online
Apply Date : ASAP
Synopsys, Inc provides products and offerings that speed up innovation within the global electronics market. As a chief in electronic design automation (EDA) and semiconductor intellectual property (IP), Synopsys’ complete, built-in portfolio of approach-stage, IP, implementation, verification, manufacturing, optical and discipline-programmable gate array (FPGA) solutions support handle the important thing challenges designers face comparable to energy and yield management, process-to-silicon verification and time-to-results. These technological know-how-leading solutions support give Synopsys purchasers a aggressive side in quickly bringing the first-rate merchandise to market even as lowering expenditures and agenda risk.
* Candidate should be BE/B Tech from a recognised university.
* Should have an aggregate of 60% through out academics.
* Must have knowledge on CMOS fundamentals
* Should have knowledge on digital Design fundamentals
* Must work on RC circuits
* Must setup and Hold Time Concepts
* Should perform circuit Simulations
* Must perform compiler QA and Release
* Must have design QA
* Must get trained to perform penetration testing or vulnerability assessment of web, mobile applications, and networks
* Should get trained to perform static source code analysis
* Must research and enhance the solution features, assist with applications / tools
* Must have understanding of OWASP Top 10
* Must have relevant Security Industry certifications (CEH/OSCP) will be an added advantage
* Should have knowledge of Mobile application development
* Should work on a designated project (s) independently and / or with minimum supervision
* Should be able to assist the Consultants with developing scripts for automation of process, tools, and frameworks.
* Must have basic knowledge of SRAM bitcell
* Should have basic knowlwedge of memory architecture
* Must have basic knowledge of memory timing arcs